Field of the Disclosure
The present disclosure relates to a display device, and more particularly to a gate driver and a display device including the same. Although the present disclosure is suitable for a wide scope of applications, it is particularly suitable for a gate driver with a reduced bezel size by reducing the number of thin-film transistors.
Description of the Background
As a variety of portable electronic devices such as mobile terminals and laptop computers have been developed, demands toward flat panel display devices employed by such devices are increasing.
Research is ongoing into the flat panel display devices, including liquid-crystal display (LCD) devices, plasma display panel (PDP) devices, field emission display (FED) devices, and organic light-emitting diode display (OLED) devices.
Among these flat panel display devices, an LCD device finds more applications since it can be produced in large quantity, can be driven easily, and can achieve high image quality and a large screen.
FIG. 1 is a view showing a display device in the background art.
Referring to FIG. 1, an LCD device display images by adjusting transmittance in each of pixels depending on an input image signal. To this end, the display device includes a display panel 10 in which liquid-crystal cells are arranged in a matrix form, a backlight unit (not shown) for supplying light to the display panel 10, and a driving circuitry for driving the display panel 10 and the backlight unit.
The display panel 10 further includes an active area 20 where images are displayed, and a pad area 30 where no image is displayed and a gate driver 60 and a data pad 40 are formed.
The driving circuitry includes a timing controller, a data driver 50 and the gate driver 60. The data pad 40 is disposed on the upper end or the lower end of the pad area 30. The data driver 50 may be disposed on a printed circuit board (PCB) or a chip-on-film (COF) and may be connected to the data pad 40 via a flexible printed circuit (FPC).
The gate driver 60 sequentially applies scan signals (i.e., gate driving signals) for turning on thin-film transistors formed in the pixels to a plurality of gate lines, respectively. By doing so, the pixels in the display panel 10 are driven sequentially.
To this end, the gate driver 60 includes a shift resister, and a level shift that converts an output signal from the shift register into a signal having a swing width appropriate for driving the thin-film transistors.
A gate-in-panel (GIP) structure is employed, in which thin-film transistors TFT are formed on a lower substrate (array substrate) of the display panel 10 using amorphous silicon a-Si, and the gate driver 60 is integrated with the display panel (i.e., the gate driver 60 is disposed in the display panel). The GIP type gate driver 60 may be disposed on either side of the pad area of the array substrate.
FIG. 2 is a diagram showing four channels of a GIP in the background art. FIG. 3 is a diagram showing a GIP circuit of a display device in the background art.
Referring to FIGS. 2 and 3, the GIP type gate driver 60 in the background art includes a plurality of stages to generate scan signals to apply to the gate lines, respectively. Each of the plurality of stages becomes a channel of the gate driver.
The GIP type gate driver 60 applies scan signals to the gate lines via a plurality of channels. Among all of the channels of the gate driver 60, every two channels share a QB-node, and each of the channels has a Q-node. To apply a scan signal to a gate line, each of the channels of the gate driver 60 includes seventeen transistors TR.
The gate driver circuit repeats a precharging operation of applying voltage at high level to a Q node upon receiving an input signal VST, a charging operation in which the output from the gate driver is changed from low to high level, a discharging operation in which the output is changed from high to low level, and a holding interval in which the output remains at low level. In doing so, the output of each of the channels is precharged and output by the respective Q node.
A transistor T1 of the first channel and another transistor T1 of the second channel are reset transistors, which are reset upon receiving a reset signal. A transistor T2 of the first channel and another transistor T2 of the second channel receive outputs from different stages as a signal VST1 and are turned on at different timings. A transistor T15 is a pull-up transistor, which is turned on upon receiving an output from the transistor T1 to output voltage VSS, or is turned on and by bootstrapping with an output from the transistor T2 and a clock signal CLK to output an output voltage Vout, i.e., a scan signal.
In the gate driver 60 shown in FIGS. 2 and 4, the Q node is divided into Q1 and Q2 such that they are operated separately, and two channels share a QB node such that discharging of the Q node and the holding of the output voltage are controlled.
In the GIP circuit in the background art, seventeen transistors are required to obtain output from a stage, and sixty-eight transistors are required to obtain output from four stages.
For full-HD resolution with 1,920 channels, 32,640 transistors are required for a GIP circuit, which is calculated by multiplying the number of transistors per stage, 17 by the number of the entire channels, 1,920. As a result, the size of the GIP formed in the pad area, which is the inactive area, is increased. For U-HD resolution, the number of transistors in the GIP circuit is doubled, and accordingly the size of the GIP formed in the pad area is further increased.
The size of the bezel surrounding the inactive area is determined depending on the size of the GIP, and thus the size of the bezel increases with the size of the GIP. As a result, the aesthetic design of the display device deteriorates.
In addition, in the background art, the size of the bezel is large, such that the number of panels that can be fabricated from a mother substrate at a time is reduced.